The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

May. 07, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chang Woo Noh, Hwaseong-si, KR;

Myung Gil Kang, Suwon-si, KR;

Geum Jong Bae, Suwon-si, KR;

Dong Il Bae, Seongnam-si, KR;

Jung Gil Yang, Hwaseong-si, KR;

Sang Hoon Lee, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/033 (2006.01); H01L 21/8238 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/0337 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01);
Abstract

Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.


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