The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Sep. 24, 2019
Applicant:

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Hubei, CN;

Inventors:

Beibei Sheng, Hubei, CN;

Sheng Hu, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/7684 (2013.01); H01L 21/7685 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01);
Abstract

A semiconductor device and a method for manufacturing the same. When a pattern for etching is formed through photolithography after forming a photoresist layer on an adhesion layer, a sub-resolution auxiliary pattern of the mask is above the non-lead-out region, and an exposable pattern of the mask is above a lead-out region. In the photolithography, a first partial exposure region exposed partially in depth is formed in the photoresist layer corresponding to the sub-resolution auxiliary pattern, and an exposed pattern that is exposed completely is formed in the photoresist layer corresponding to the exposable pattern. After anisotropic etching on the adhesion layer through the photoresist layer, both an opening running through a partial thickness of the adhesion layer and a via hole running through the adhesion layer are formed. The opening balances a load in planarization during a process of filling the via hole.


Find Patent Forward Citations

Loading…