The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2021
Filed:
Apr. 04, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Wei Wu, Portland, OR (US);
Rajesh Sundaram, Folsom, CA (US);
Chetan Chauhan, Folsom, CA (US);
Jawad B. Khan, Portland, OR (US);
Shigeki Tomishima, Portland, OR (US);
Srikanth Srinivasan, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G06F 3/0619 (2013.01); G06F 3/0644 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/1048 (2013.01);
Abstract
Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.