The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Jun. 27, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Matthew Lee, Chandler, AZ (US);

Benedict C. Ofuonye, Chandler, AZ (US);

Erich Ewy, Chandler, AZ (US);

Jeffrey Willcoxon, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/71 (2020.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
G01R 31/71 (2020.01); G01R 31/2853 (2013.01); H01L 23/49816 (2013.01); G01R 31/2879 (2013.01); G01R 31/2896 (2013.01); H05K 2203/041 (2013.01);
Abstract

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.


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