The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Apr. 13, 2020
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Mu-Shun Lee, Taipei, TW;

Yang-Ming Chen, Taipei, TW;

Youxin Gao, Mountain View, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/165 (2006.01); G01R 31/40 (2020.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
G01R 19/16571 (2013.01); G01R 19/0084 (2013.01); G01R 19/16523 (2013.01); G01R 31/40 (2013.01);
Abstract

A system is disclosed that includes a memory and a processor to perform operations, including analyzing rail voltage drop for a full-chip to identify an IR drop violation in a block design of the full-chip. The operations include performing a block-level rail voltage drop analysis for the block design and generating a revised block design corresponding to the block design in which the IR drop violation is identified. The operations include performing a block-level rail voltage drop analysis on the revised block design to verify that the IR drop violation is fixed and integrating the revised block design into the full-chip to replace the block design upon verifying that the IR drop violation is fixed. The operations include performing the rail voltage drop analysis for the full-chip comprising the revised block design.


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