The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2021
Filed:
Nov. 11, 2016
Applicants:
Imec Vzw, Leuven, BE;
Vrije Universiteit Brussel, Brussels, BE;
Inventors:
Assignees:
IMEC vzw, Leuven, BE;
Vrije Universiteit Brussel, Brussels, BE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 27/11 (2006.01); H01L 29/775 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); H01L 27/06 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); B82Y 10/00 (2013.01); H01L 27/0688 (2013.01); H01L 27/1104 (2013.01); H01L 29/0676 (2013.01); H01L 29/66439 (2013.01); H01L 29/66666 (2013.01); H01L 29/775 (2013.01); H01L 29/7869 (2013.01); H01L 29/78642 (2013.01); H01L 29/41733 (2013.01);
Abstract
The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.