The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2021
Filed:
Dec. 05, 2019
Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;
Zhonghua Li, Shanghai, CN;
Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;
Abstract
The invention discloses a P-type MOSFET, a channel region consisting of an N-well is formed in the semiconductor substrate covered with a gate structure; the N-well is formed by overlaying an annealed phosphorus-implanted region, an annealed first arsenic-implanted region and an annealed second arsenic-implanted region, and the first arsenic-implanted region and the second arsenic-implanted region are overlaid to form a threshold voltage regulation region; the implantation depth of the first arsenic-implanted region is greater than that of the second arsenic-implanted region; and an amorphous layer is formed by the first arsenic-implanted region on the semiconductor substrate to improve the implantation uniformity of the second arsenic-implanted region and to decrease the peak surface doping concentration of the second arsenic-implanted region located on the surface of the semiconductor substrate. The invention further discloses a method for manufacturing a P-type MOSFET. The invention can reduce the flicker noises of a device.