The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Mar. 12, 2020
Applicant:

Zhuhai Chuangfeixin Technology Co., Ltd., Zhuhai, CN;

Inventors:

Li Li, Femont, CA (US);

Zhigang Wang, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/112 (2006.01); H01L 29/10 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 29/1083 (2013.01); H01L 29/6659 (2013.01); H01L 29/66537 (2013.01); H01L 29/7833 (2013.01);
Abstract

An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.


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