The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Oct. 23, 2019
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventor:

Chih-Hsin Chen, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/14 (2006.01); H01L 27/11519 (2017.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0433 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01);
Abstract

A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.


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