The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Nov. 08, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Hyun Jun Yoon, Changwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 7/06 (2006.01); G11C 11/56 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4087 (2013.01); G11C 7/065 (2013.01); G11C 11/4074 (2013.01); G11C 11/4082 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/5642 (2013.01);
Abstract

A nonvolatile memory device includes a memory cell array that includes memory cells arranged in rows and columns, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines and includes first transistors configured to sense voltages of the bit lines and second transistors configured to invert and sense the voltages of the bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted.


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