The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Nov. 01, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Sree Rkc Saraswatula, Hyderabad, IN;

Narendra Kumar Pulipati, Hyderabad, IN;

Santosh Yachareni, Hyderabad, IN;

Shidong Zhou, Milpitas, CA (US);

Sundeep Ram Gopal Agarwal, Hyderabad, IN;

Brian Gaide, Erie, CO (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 29/50 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G11C 5/148 (2013.01); G11C 29/50 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Examples described herein provide a method for disabling a defective portion of a fabric die of a stacked IC device. The method includes receiving a signal indicating that a portion of a fabric die of a stacked IC device including at least two fabric dies is defective. The method further includes, in response to the signal, pulling a source voltage rail of the defective portion to ground, thereby disabling the portion, and operating the remainder of the fabric die without interference from or contention with the disabled portion. In one example, the stacked IC device is an active on active (AoA) device, and the portion of the fabric die includes a configuration memory cell. In one example, the signal is received after power-up of the stacked IC device.


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