The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Dec. 04, 2019
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Ashwani Kumar Sanwal, Barnota Dom, IN;

Vandana Gupta, Delhi, IN;

Devendra Deshpande, Noida, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 3/0482 (2013.01); G06F 3/0484 (2013.01); G06F 30/31 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 3/0482 (2013.01); G06F 3/04845 (2013.01); G06F 30/31 (2020.01);
Abstract

Embodiments disclosed are directed to systems and methods for modifying an electronic circuit design. According to embodiments, the method includes generating a circuit element of an electronic circuit layout on a graphical user interface, and generating an array group including a plurality of circuit elements. Each cell of the array group includes the same circuit element, and the array group is generated such that a change in at least one attribute of the array group is applied to each circuit element of the plurality of circuit elements.


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