The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2021
Filed:
Jan. 12, 2018
Method, apparatus, and system for power management on a cpu die via clock request messaging protocol
Intel Corporation, Santa Clara, CA (US);
Poh Thiam Teoh, Penang, MY;
Mikal C. Hunsaker, El Dorado Hills, CA (US);
Su Wei Lim, Penang, MY;
Gim Chong Lee, Pulau Pinang, MY;
Hooi Kar Loo, Penang, MY;
Shashitheren Kerisnan, Penang, MY;
Siang Lin Tan, Bayan Lepas, MY;
Ming Chew Lee, Pulau Pinang, MY;
Ngeok Kuan Wai, Johor, MY;
Li Len Lim, Johor, MY;
Intel Corporation, Santa Clara, CA (US);
Abstract
Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.