The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Oct. 15, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Nan Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01); H01L 21/0214 (2013.01); H01L 21/0228 (2013.01); H01L 21/0262 (2013.01); H01L 21/02527 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a device region for forming devices and isolation regions located on two sides of the device region; patterning the base to form a substrate and fins protruding from the substrate; forming, on two sides of the device region, first dummy fins protruding from the substrate of the isolation region; and forming an isolation layer on the substrate exposed by the fins and the first dummy fins, where the isolation layer covers a part of side walls of the fin. In some implementations of the present disclosure, the setting of the first dummy fins improves the uniformity of pattern density in peripheral regions for each fin, which is advantageous for improving the thickness uniformity of an isolation layer in the device region, reducing the probability that the fin is bent or tilted, and improving electrical properties of the semiconductor structure.


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