The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Aug. 02, 2019
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Jin Jisong, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 29/40 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41725 (2013.01); H01L 21/0228 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, a dummy gate structure being formed on the base, and a source/drain doped layer being formed within the base on both sides of the dummy gate structure; forming a first dielectric layer on the base exposed from the dummy gate structure, the first dielectric layer exposing a portion of a side wall of the dummy gate structure; forming a self-aligned stop layer on at least the side wall of the dummy gate structure exposed from the first dielectric layer; after the self-aligned stop layer is formed, forming a second dielectric layer on the first dielectric layer, and the second dielectric layer and the first dielectric layer being used as interlayer dielectric layers; after the second dielectric layer is formed, replacing the dummy gate structure with a gate structure; etching the interlayer dielectric layer between self-aligned stop layers on side walls of the adjacent gate structures to form a contact exposing the top of the source/drain doped layer; and forming, within the contact, a contact plug electrically connected to the source/drain doped layer. The present disclosure reduces process difficulty in forming a self-aligned contact plug and simplifies a process flow.


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