The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Sep. 17, 2019
Applicant:

Toyoda Gosei Co., Ltd., Kiyosu, JP;

Inventors:

Kota Yasunishi, Kiyosu, JP;

Toru Oka, Kiyosu, JP;

Kazuya Hasegawa, Kiyosu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/2003 (2013.01); H01L 29/66143 (2013.01); H01L 29/66212 (2013.01); H01L 29/872 (2013.01);
Abstract

The likelihood of formation of a corner resulting from a recess in a part of an n-type semiconductor layer is reduced at a deeper position than a p-type semiconductor layer. A method of manufacturing a semiconductor device comprises: forming a gallium nitride (GaN) based n-type semiconductor layer containing n-type impurities; forming a groove by forming a first mask on a part of a surface of the n-type semiconductor layer and then etching a part uncovered by the first mask; removing the first mask; forming a gallium nitride (GaN) based p-type semiconductor layer containing p-type impurities on the surface of the n-type semiconductor layer including the groove; etching the p-type semiconductor layer so as to expose the n-type semiconductor layer at least in a range differing from a range in the presence of the groove; and forming a metal electrode contacting the exposed n-type semiconductor layer and the p-type semiconductor layer.


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