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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11011535 B1

PDFFull Text
Date of Patent:
May. 18, 2021

Filed:

Dec. 22, 2019

Semiconductor device with integrated memory devices and mos devices and process of making the same

Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wang Xiang, Singapore, SG;

Chia-Ching Hsu, Yunlin County, TW;

Shen-De Wang, Hsinchu County, TW;

Weichang Liu, Singapore, SG;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Attorney:

Winston Hsu

Primary Examiner:

David Vu

Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/3213 (2006.01); H01L 21/027 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/0217 (2013.01); H01L 21/0274 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/28035 (2013.01); H01L 21/28167 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

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