The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Dec. 29, 2017
Applicant:

Fudan University, Shanghai, CN;

Inventors:

Shijin Ding, Shanghai, CN;

Shibing Qian, Shanghai, CN;

Wenjun Liu, Shanghai, CN;

Wei Zhang, Shanghai, CN;

Assignee:

Fudan University, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/465 (2006.01); H01L 21/4763 (2006.01); H01L 29/24 (2006.01); H01L 29/45 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); G11C 11/5671 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H01L 21/0228 (2013.01); H01L 21/02068 (2013.01); H01L 21/0274 (2013.01); H01L 21/02175 (2013.01); H01L 21/02194 (2013.01); H01L 21/02266 (2013.01); H01L 21/02565 (2013.01); H01L 21/465 (2013.01); H01L 21/47635 (2013.01); H01L 29/24 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/45 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/7923 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01);
Abstract

A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density.


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