The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 2021
Filed:
Apr. 20, 2020
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Shahaji B. More, Hsinchu, TW;
Zheng-Yang Pan, Zhubei, TW;
Shih-Chieh Chang, Taipei, TW;
Chun-Chieh Wang, Kaohsiung, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823857 (2013.01); H01L 21/02148 (2013.01); H01L 21/02164 (2013.01); H01L 21/02181 (2013.01); H01L 21/02192 (2013.01); H01L 21/28088 (2013.01); H01L 21/823821 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/42364 (2013.01); H01L 29/4966 (2013.01); H01L 29/511 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 21/0228 (2013.01); H01L 21/02271 (2013.01); H01L 21/28194 (2013.01); H01L 21/823418 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01); H01L 29/7848 (2013.01);
Abstract
A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.