The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Sep. 03, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Injo Ok, Loudonville, NY (US);

Balasubramanian Pranatharthiharan, Watervliet, NY (US);

Soon-Cheon Seo, Glenmont, NY (US);

Charan V. Surisetty, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 21/31 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/31 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 21/823437 (2013.01); H01L 27/088 (2013.01); H01L 29/42356 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01);
Abstract

Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.


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