The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Nov. 29, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Manish Arora, Hsinchu, TW;

Hung-Jen Liao, Hsinchu, TW;

Yen-Huei Chen, Jhudong Township, TW;

Nikhil Puri, Hsinchu, TW;

Yu-Hao Hsu, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/24 (2006.01); H01L 27/11551 (2017.01); G11C 7/12 (2006.01); G11C 16/04 (2006.01); G11C 11/00 (2006.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 7/12 (2013.01); G11C 11/005 (2013.01); G11C 16/0483 (2013.01); H01L 27/11524 (2013.01); H01L 27/11551 (2013.01);
Abstract

A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.


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