The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2021
Filed:
Nov. 20, 2019
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventor:
Seung Yeop Lee, Suwon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/45 (2013.01); H01L 24/73 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/73257 (2013.01); H01L 2924/18165 (2013.01);
Abstract
A stack package includes a package substrate and a fan-out sub-package mounted on the package substrate using first and second connection bumps. The fan-out sub-package includes a first semiconductor die and redistributed line (RDL) patterns. Second semiconductor dies are stacked on the package substrate to provide a first step structure, and third semiconductor dies are stacked on the second semiconductor dies to provide a second step structure. The second and third semiconductor dies are connected to the package substrate by bonding wires.