The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Apr. 23, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Chen Wu, Leuven, BE;

Peter Rabkin, Cupertino, CA (US);

Masaaki Higashitani, Cupertino, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 25/00 (2006.01); H01L 27/11556 (2017.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/02203 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53257 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/48 (2013.01); H01L 24/89 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76819 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/80001 (2013.01); H01L 2924/1438 (2013.01);
Abstract

First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.


Find Patent Forward Citations

Loading…