The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Jul. 23, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Juergen Hoegerl, Regensburg, DE;

Tao Hong, Soest, DE;

Tino Karczewski, Sinzing, DE;

Matthias Lassmann, Lippstadt, DE;

Christian Schweikert, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/34 (2006.01); H01L 23/367 (2006.01); H01L 23/492 (2006.01); H01L 23/373 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/433 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/3735 (2013.01); H01L 23/433 (2013.01); H01L 23/492 (2013.01); H01L 23/49524 (2013.01);
Abstract

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.


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