The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Jun. 04, 2019
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Hemant Mungekar, Campbell, CA (US);

Ganesh Balasubramanian, Fremont, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J 37/32 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H01L 21/68 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67259 (2013.01); H01J 37/32174 (2013.01); H01J 37/32715 (2013.01); H01J 37/32926 (2013.01); H01L 21/67253 (2013.01); H01L 21/67288 (2013.01); H01L 21/68 (2013.01); H01L 21/6833 (2013.01); H01L 22/14 (2013.01);
Abstract

Methods and systems of detection of wafer placement error in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when a wafer placement error is detected. The method—is based on measuring a slope of current in an electrostatic chuck (ESC), which is correlated to lack of contact between the wafer and the ESC. Wafer placement detection at an early stage, when a heater and an ESC are being set up, gives the option of stopping the process before high power RF plasma is created.


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