The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2021
Filed:
May. 08, 2020
Winbond Electronics Corp., Taichung, TW;
Young-Tae Kim, San Ramon, CA (US);
Chan-Seok Park, San Jose, CA (US);
Youngjoo Choi, San Jose, CA (US);
Myung-Chan Choi, San Jose, CA (US);
Winbond Electronics Corp., Taichung, TW;
Abstract
A latency control circuit and method are provided. The latency control circuit includes a DLL circuit, a latency counter circuit, a synchronization circuit, and a delay line circuit. The DLL circuit enters an inactive state after locking the delay time and provides an active signal at a disable state, delay locking information and loop delay information during the inactive state. The synchronization circuit stops providing a first clock signal according to the active signal at the disable state and then synchronously outputs an operation enabling signal and a second clock signal in response to an enablement of the operation signal. The delay line circuit receives the delay locking information, the operation enabling signal, and the second clock signal and outputs an operation delay signal and an output clock signal after the delay time.