The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Jul. 31, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Kayoko Shibata, Hachioji, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); G11C 5/06 (2006.01); G11C 5/14 (2006.01); G11C 11/4072 (2006.01); H01L 27/06 (2006.01); G11C 11/4074 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 5/14 (2013.01); G11C 11/4072 (2013.01); G11C 11/4074 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 27/10897 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.


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