The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Apr. 12, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Mohammad Abdallah, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); H04L 12/28 (2006.01); G06F 12/00 (2006.01); G06F 9/46 (2006.01); G06F 15/173 (2006.01); G06F 9/30 (2018.01); G06F 13/00 (2006.01); H04L 12/933 (2013.01); G06F 12/0886 (2016.01); G06F 12/0853 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3885 (2013.01); G06F 9/3004 (2013.01); G06F 9/3853 (2013.01); G06F 9/462 (2013.01); G06F 12/00 (2013.01); G06F 12/0853 (2013.01); G06F 12/0886 (2013.01); G06F 13/00 (2013.01); G06F 15/17318 (2013.01); H04L 12/28 (2013.01); H04L 49/1523 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/1056 (2013.01);
Abstract

A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.


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