The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Jun. 13, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Kazuhiko Kajigaya, Saitama, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 14/00 (2006.01); G11C 11/22 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 7/06 (2006.01); G11C 7/14 (2006.01); G06F 12/02 (2006.01); G11C 11/00 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0027 (2013.01); G06F 12/02 (2013.01); G06F 12/0215 (2013.01); G11C 7/065 (2013.01); G11C 7/1006 (2013.01); G11C 7/1015 (2013.01); G11C 7/1051 (2013.01); G11C 7/1072 (2013.01); G11C 7/1078 (2013.01); G11C 7/14 (2013.01); G11C 7/22 (2013.01); G11C 11/005 (2013.01); G11C 11/221 (2013.01); G11C 11/2273 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/205 (2013.01); G11C 2207/005 (2013.01);
Abstract

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.


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