The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

May. 05, 2020
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Fu-Chin Tsai, Hsinchu, TW;

Chun-Chi Yu, Hsinchu, TW;

Chih-Wei Chang, Hsinchu, TW;

Gerchih Chou, San Jose, CA (US);

Kuo-Wei Chi, Hsinchu, TW;

Shih-Chang Chen, Hsinchu, TW;

Shih-Han Lin, Hsinchu, TW;

Min-Han Tsai, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); H03K 7/08 (2006.01); G11C 8/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 8/18 (2013.01); H03K 7/08 (2013.01);
Abstract

The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.


Find Patent Forward Citations

Loading…