The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2021
Filed:
Dec. 19, 2019
Cadence Design Systems, Inc., San Jose, CA (US);
Mitchell Poplack, San Jose, CA (US);
Xiaolei Guo, San Jose, CA (US);
Phung Truong, San Jose, CA (US);
Justin Schmelzer, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An emulation system may include an emulator. The emulator may include at least one chip and at least one FPGA. The chip may be associated with the FPGA. The FPGA may operate as a coprocessor to implement in-system scan test of the chip. In a scan mode of the in-system scan test, the coprocessor may transmit one or more in-system test instructions to the chip through its existing connections with the chip. The coprocessor may capture test response data from the chip in response to the one or more in-system test instructions through its existing connections with the chip. In an offline mode, the coprocessor may compare the test response data with expected response data to determine if the chips are functioning correctly.