The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Nov. 06, 2018
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Edward Mottram, Cambridge, GB;

Matthew David Eaton, Cambridge, GB;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01);
Abstract

For a division of a dividend by a constant divider, a circuit architecture may calculate partial remainders. The circuit architecture may implement a tree structure to generate intermediate signals of partial remainders and combine adjacent intermediate signals to generate other partial remainders downstream. The circuit architecture may generate a quotient based on the partial remainders. The circuit architecture may also implement bit shifting and zero-padding on left side of the dividend to generate bit-level partial remainders. Furthermore, the circuit architecture may enable a fast round-to-zero division of signed integers by flipping the input bits of a negative integer and output bits of the corresponding quotient and performing only one increment operation, either before the division or after the division. In addition, the circuit architecture may also perform a division of a dividend in a carry-save form.


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