The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Nov. 19, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Frederico C. Pratas, Mirandela, ES;

Ayose J. Falcon, Barcelona, ES;

Marc Lupon, Barcelona, ES;

Fernando Latorre, Cambridge, GB;

Pedro Lopez, Barcelona, ES;

Enric Herrero Abellanas, Barcelona, ES;

Georgios Tournavitis, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/15 (2006.01); G06N 3/063 (2006.01); G06F 12/0862 (2016.01); G06F 12/0875 (2016.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
G06F 17/153 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/6026 (2013.01);
Abstract

An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.


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