The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Mar. 15, 2017
Vertically stacked devices with self-aligned regions formed by direct self assembly (dsa) processing
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Aaron D. Lilak, Beaverton, OR (US);
Patrick Theofanis, Portland, OR (US);
Cory E. Weber, Hillsboro, OR (US);
Stephen M. Cea, Hillsboro, OR (US);
Rishabh Mehandru, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/105 (2006.01); H01L 21/32 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); H01L 21/32 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/7827 (2013.01);
Abstract
An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.