The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Sep. 18, 2019
Alpha and Omega Semiconductor (Cayman), Ltd., Grand Cayman, KY;
Yan Xun Xue, Los Gatos, CA (US);
Yueh-Se Ho, Sunnyvale, CA (US);
Long-Ching Wang, Cupertino, CA (US);
Madhur Bobde, Sunnyvale, CA (US);
Xiaobin Wang, San Jose, CA (US);
Lin Chen, San Jose, CA (US);
ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD., Grand Cayman, KY;
Abstract
A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a 'drain 1, drain 2, drain 1, and drain 2' pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.