The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Dec. 16, 2019
Cadence Design Systems, Inc., San Jose, CA (US);
Georgia Penido Safe, Belo Horizonte, BR;
Vincent Gregory Reynolds, Maidenhead, GB;
Adriana Cassia Rossi de Almeida Braz, Brasilia, BR;
Julio Alexandre Silva Rezende, Belo Horizonte, BR;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.