The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Dec. 19, 2019
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Mitchell Poplack, San Jose, CA (US);
Yuhei Hayashi, San Jose, CA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 9/455 (2018.01); G06F 7/58 (2006.01); G06F 11/10 (2006.01); G06F 30/333 (2020.01); G06F 30/331 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 7/584 (2013.01); G06F 9/45508 (2013.01); G06F 11/1004 (2013.01); G06F 30/331 (2020.01); G06F 30/333 (2020.01);
Abstract
An emulation system may have a built-in self-test circuit to generate one or more built-in self-test instructions. The one or more built-in self-test instructions may be pseudorandom. The one or more built-in self-test instructions may cause one or more emulation processors of the emulation system to generate one or more deterministic outputs. A testing processor of the emulation system may compare the one or more deterministic outputs to detect a faulty emulation processor, a faulty emulation processor cluster, or a faulty emulation chip of the emulation system.