The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Sep. 10, 2020
Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);
Brian A. Saari, Manassas, VA (US);
Stephen A. Chadwick, Bristow, VA (US);
Jason T. Dowling, Ijamsville, MD (US);
Michael J. Frack, Reva, VA (US);
David D. Moser, Haymarket, VA (US);
Mark R. Shaffer, Culpeper, VA (US);
BAE Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);
Abstract
An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.