The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Dec. 17, 2019
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

William Robert Reece, Over, GB;

Thomas Andrew Newton, Great Cambourne, GB;

Zhuo Li, Austin, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 30/398 (2020.01);
Abstract

Electronic design automation systems, methods, and media are presented for cell cloning during circuit design. In one embodiment, for a circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree, a delay is identified for each flip-flop element. The flip-flop elements are clustered by delay to generate at least two clusters of flip-flop elements. Elements within the clusters are then grouped by physical characteristics to generate delay groups of flip-flop elements. An updated routing tree is then generated for the circuit design using the first delay group and the second delay group.


Find Patent Forward Citations

Loading…