The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Apr. 24, 2012
Applicant:

Peter P. Waskiewicz, Jr., Portland, OR (US);

Inventor:

Peter P. Waskiewicz, Jr., Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 13/24 (2006.01); G06F 1/3203 (2019.01); G06F 1/329 (2019.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3861 (2013.01); G06F 1/3203 (2013.01); G06F 1/329 (2013.01); G06F 9/4812 (2013.01); G06F 13/24 (2013.01); Y02D 10/00 (2018.01);
Abstract

Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores. In response to detecting cores emerging from idle states, reconfiguration of interrupt vectors can be performed to rebalance the assignment of the vectors across active cores by remapping a portion of the vectors to those cores.


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