The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Mar. 30, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Amit Gradstein, Binyamina, IL;

Simon Rubanovich, Haifa, IL;

Sagi Meller, Zichron Yaakov, IL;

Zeev Sperber, Zichron Yackov, IL;

Jose Yallouz, Haifa, IL;

Robert Valentine, Kiryat Tivon, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/3001 (2013.01); G06F 9/30109 (2013.01); G06F 9/3877 (2013.01); G06F 17/16 (2013.01);
Abstract

Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits; a first plurality of registers that represents an input two-dimensional matrix coupled to the matrix operations accelerator circuit; a decoder, of a core coupled to the matrix operations accelerator circuit, to decode an instruction into a decoded instruction; and an execution circuit of the core to execute the decoded instruction to cause the two-dimensional grid of fused multiply accumulate circuits to form a transpose of the input two-dimensional matrix when the matrix operations accelerator circuit is in a transpose mode.


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