The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Apr. 09, 2020
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wei-Ming Ku, Hsinchu County, TW;

Wein-Town Sun, Hsinchu County, TW;

Ying-Je Chen, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); H03K 19/00 (2006.01); H03K 17/16 (2006.01); H03K 19/0185 (2006.01); H03K 3/356 (2006.01); H03K 19/0944 (2006.01); G05F 3/26 (2006.01); H02M 3/07 (2006.01); H03K 17/687 (2006.01); G11C 5/02 (2006.01); G11C 11/16 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); G05F 3/262 (2013.01); G11C 5/025 (2013.01); G11C 7/06 (2013.01); G11C 7/1051 (2013.01); G11C 7/1084 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H02M 3/07 (2013.01); H03K 3/356 (2013.01); H03K 17/162 (2013.01); H03K 17/6871 (2013.01); H03K 19/018528 (2013.01); H03K 19/0944 (2013.01); G05F 3/267 (2013.01);
Abstract

A random code generator includes a memory cell, two write buffers and two sensing circuits. The memory cell includes a first program path between a first source line and a first bit line, a second program path between the first source line and a second bit line, a first read path between a second source line and a third bit line, and a second read path between a third source line and a fourth bit line. The two write buffers are connected with the first bit line and the second bit line, respectively. The two sensing circuits are connected with the third bit line and the fourth bit line, respectively. The two sensing circuits generate a first output signal and the second output signal to the corresponding write buffers according to the read currents in the corresponding read paths.


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