The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Oct. 24, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Keng-Ping Lin, Taichung, TW;

Tzu-Ming Ou Yang, Taichung, TW;

Shu-Ming Li, Taichung, TW;

Tetsuharu Kurokawa, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/308 (2006.01); H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 21/70 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 21/3086 (2013.01); H01L 21/762 (2013.01); H01L 27/10 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a plurality of gate structures, a plurality of dielectric structures, and spacers. The plurality of gate structures is disposed on the substrate. The plurality of dielectric structures is respectively disposed between the gate structures and the substrate, wherein a top width of the dielectric structure is less than the bottom width of the dielectric structure. The spacers are disposed on the sidewalls of the gate structures and cover the sidewalls of the dielectric structures.


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