The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Aug. 14, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Zhao Hui Tang, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/06 (2006.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/02282 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/31111 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 27/0688 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 29/1037 (2013.01); H01L 29/40117 (2019.08); H01L 29/66545 (2013.01);
Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a first dielectric layer, and a second dielectric layer. The memory stack includes interleaved conductor layers and dielectric layers above the substrate. The memory stack includes a staircase structure at one edge of the memory stack. The channel structure extends vertically through the memory stack. The first dielectric layer is above the memory stack. A part of the first dielectric layer right above the staircase structure has a dished bottom surface. The second dielectric layer is on the part of the first dielectric layer right above the staircase structure and has a nominally flat top surface.


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