The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Jan. 10, 2018
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Ahmed Y. Ginawi, South Burlington, VT (US);

Andreas D. Stricker, Essex Junction, VT (US);

Alain F. Loiseau, Williston, VT (US);

Ephrem G. Gebreselasie, South Burlington, VT (US);

Joseph M. Lukaitis, Pleasant Valley, NY (US);

Richard A. Poro, III, Bristol, VT (US);

Assignee:

Marvell Asia Pte., Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0266 (2013.01); H01L 27/0285 (2013.01); H01L 27/0292 (2013.01); H01L 27/0296 (2013.01); H02H 9/044 (2013.01); H02H 9/046 (2013.01);
Abstract

The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.


Find Patent Forward Citations

Loading…