The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Jul. 23, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Juergen Hoegerl, Regensburg, DE;

Ordwin Haase, Taufkirchen, DE;

Tobias Kist, Effeltrich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/4853 (2013.01); H01L 21/4871 (2013.01); H01L 21/565 (2013.01); H01L 22/32 (2013.01); H01L 23/3121 (2013.01); H01L 23/3675 (2013.01); H01L 23/3735 (2013.01); H01L 24/32 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/14252 (2013.01);
Abstract

A semiconductor package having a double-sided cooling structure includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a shielding structure configured to electromagnetically shield a line of the semiconductor package.


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