The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Jul. 03, 2019
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventor:

Donald Ray Disney, Malta, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 21/8238 (2006.01); H02M 3/158 (2006.01); H05K 1/02 (2006.01); H01L 29/20 (2006.01); H01L 23/34 (2006.01); H01L 23/36 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 21/823871 (2013.01); H01L 23/34 (2013.01); H01L 23/36 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 29/2003 (2013.01); H02M 3/1582 (2013.01); H05K 1/0203 (2013.01);
Abstract

Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate, a plurality of transistors overlying the semiconductor substrate, and an interlayer dielectric layer overlying the plurality of transistors with a metallization layer disposed within the interlayer dielectric layer. The plurality of transistors and the metallization layer form a gate driver circuit. The integrated circuit further includes a plurality of vias disposed through the interlayer dielectric layer, a gate driver electrode coupled to the gate driver circuit, a III-V device electrode overlying and coupled to the gate driver electrode, and a III-V device overlying and coupled to the III-V device electrode.


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