The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Aug. 24, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andrew Greene, Albany, NY (US);

Victor W. C. Chan, Guilderland, NY (US);

Gangadhara Raja Muthinti, Albany, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/8238 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/28 (2006.01); H01L 27/092 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/28247 (2013.01); H01L 21/76819 (2013.01); H01L 21/76846 (2013.01); H01L 21/76865 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 23/5226 (2013.01); H01L 23/53266 (2013.01); H01L 27/0924 (2013.01);
Abstract

A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.


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