The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2021
Filed:
Dec. 22, 2017
Applicant:
Tessera, Inc., San Jose, CA (US);
Inventors:
Benjamin David Briggs, Waterford, NY (US);
Joe Lee, Albany, NY (US);
Theodorus Eduardus Standaert, Clifton Park, NY (US);
Assignee:
Tessera, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76831 (2013.01); H01L 21/76816 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/53238 (2013.01); H01L 21/76883 (2013.01);
Abstract
A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.