The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2021
Filed:
Sep. 26, 2016
Intel Corporation, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation. For example, one embodiment of a graphics processing apparatus comprises: virtualization circuitry to implement a virtualized execution environment in which a plurality of guest virtual machines (VMs) are to execute and share execution resources of the graphics processing apparatus; an input/output (I/O) memory management unit (IOMMU) to couple the VMs to one or more I/O devices; a hybrid layer address mapping (HLAM) module to combine entries from a per-process graphics translation table (PPGTT) with entries from a global graphics translation table (GGTT) into a first integrated page table, the first integrated page table mapping PPGTT guest page numbers (GPNs) to host page numbers (HPNs) and mapping GGTT virtual GPNs to HPNs; the HLAM to transform a GGTT GPN into a virtual GPN usable to access a corresponding HPN within the first integrated page table in response to a GGTT read/write operation generated by a first guest virtual machine (VM).